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Very Low Input, MHz Operation, High Efficiency Synchronous Buck
POWER MANAGEMENT Description
The SC4607 is a voltage mode step down (buck) regulator controller that provides accurate high efficiency power conversion from an input supply range of 2.25V to 5.5V. The SC4607 is capable of producing an output voltage as low as 0.5V and has a maximum duty cycle of 97%. A high level of integration reduces external component count, and makes it suitable for low voltage applications where cost, size, and efficiency are critical. The SC4607 drives external, N-channel MOSFETs with a peak gate current of 1A. The SC4607 prevents shoot through currents by offering nonoverlap protection for the gate drive signals of the external MOSFETs. The SC4607 features lossless current sensing of the voltage drop across the drain to source resistance of the high side MOSFET during its conduction period. The quiescent supply current in sleep mode is typically lower than 10A. A 1.2ms soft start is internally provided to prevent output voltage overshoot during start-up. The SC4607 is an ideal choice for converting 2.5V, 3.3V, 5V or other low input supply voltages. It's available in 10 pin MSOP package
SC4607
Features
Asynchronous start up BiCMOS voltage mode PWM controller Operation of frequency to 1MHz 2.25V to 5.5V input voltage range Output voltages as low as 0.5V +/-1% reference accuracy Sleep mode (Icc = 10A typ) Adjustable lossless short circuit current limiting Combination pulse by pulse & hiccup mode current limit High efficiency synchronous switching Up to 97% duty cycle 1A peak current driver 10-pin MSOP package
Applications
Distributed power architecture Servers/workstations Local microprocessor core power supplies DSP and I/O power supplies Battery-powered applications Telecommunications equipment Data processing applications
Typical Application Circuit
Vin = 2.25V - 5.5V
D2 R13 1 1 C3 4.7u 2 3 4 C1 180p R1 14.3k C2 2.2n C20 560pF 5 C10 1u C71 R6 U1 BST VCC ISET COMP FS/SYNC DRVH PHASE DRVL GND VSENSE 10 9 8 7 6 R5 0 M2 1.8u C6 330u C5 22u C4 22u 0 L1 M1 220u C11 22u C12 22u
R3
C14 0.1u
Vout = 1.5V (as low as 0.5V * ) / 12A
C9 4.7n R8 200
R7 10k
SC4607
*External components can be modified to provide a Vout as low as 0.5V
R9 4.99k
Revision: June 1, 2005
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SC4607
POWER MANAGEMENT Absolute Maximum Ratings
Exceeding the specifications below may result in permanent damage to the device, or device malfunction. Operation outside of the parameters specified in the Electrical Characteristics section is not implied.
Parameter Supply Voltage (VCC) Output Drivers (DRVH, DRVL) Currents Continuous P eak Inputs (VSENSE, COMP, FS/SYNC, ISET) BST PHASE PHASE Pulse tpulse < 50ns Operating Ambient Temperature Range Storage Temperature Range Junction Temperature Lead Temperature (Soldering) 10 Sec. ESD Rating (Human Body Model)
Symbol
Maximum 7 +/-0.25 +/-1.00 -0.3 to 7 13 -0.3 to 7.5 -2 to 7.5
Units V A A V V V V C C C C kV
TA TSTG TJ TLEAD ESD
-40 to +85 -65 to +150 -55 to +150 +300 4
All voltages with respect to GND. Currents are positive into, negative out of the specified terminal.
Electrical Characteristics
Unless otherwise specified, VCC = 3.3V, CT = 270pF, TA = -40C to 85C, TA=TJ
Parameter Overall Supply Voltage Supply Current, Sleep Supply Current, Operating VCC Turn-on Threshold
Test Conditions
Min
Typ
Max
Unit
5.5 FS/SYNC = 0V VCC = 5.5V TA = 25C TA = -40C to 85C 10 2 2.05 15 3.5 2.2 2.25 100
V A mA V
VCC Turn-off Hysteresis Error Amplifier VSENSE Input Voltage (Internal Reference) TA = 25C VCC = 2.25V - 5.5V, TA = 25C TA = -40C to 85C VSENSE Bias Current Open Loop Gain (1) Unity Gain Bandwidth (1) Slew Rate
(1)
mV
0.495 0.4925 0.4915
0.5 0.5
0.505 V 0.5075 0.5085
200 VCOMP = 0.5 to 2.5V 80 90 8 2.4
2
nA dB MHz V/s
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SC4607
POWER MANAGEMENT Electrical Characteristics (Cont.)
Unless otherwise specified, VCC = 3.3V, CT = 270pF, TA = -40C to 85C, TA=TJ
Parameter Error Amplifier (Cont.) VOUT High VOUT Low Oscillator Initial Accuracy Voltage Stability Temperature Coefficient Minimum Operation Frequency (1) Maximum Operation Frequency (1) Ramp Peak to Valley Ramp Peak Voltage Ramp Valley Voltage Sleep, Soft Start, Current Limit Sleep Threshold Sleep Input Bias Current Soft Start Time
(1)
Test Conditions
Min
Typ
Max
Unit
ICOMP = -5.5mA ICOMP = 5.5mA
VCC - 0.5
VCC - 0.3 0.3 0.45
V
TA = 25C TA = 25C, VCC = 2.25V to 5.5V TA = -40C to 85C
525
575 0.5 0.02
625
kHz %/V %/C kHz
50 1M 1 1.3 0.3
Hz V V V
Measured at FS VSYNC = 0V FSW = 575 KHz TJ = 25C -45 -1 1.2 -50 0.28 130
75
mV A ms
ISET Bias Current Temperature Coefficient of ISET Current Limit Blank Time Gate Drive Duty Cycle Pull-Up Resistance (DRVH) (2) Pull-Down Resistance (DRVH) Pull-Up Resistance (DRVL)
(1) (2) (1)
-55
A %/C ns
97 VBST - VPHASE = 3.3V, ISOURCE = -100mA VBST - VPHASE = 3.3V, ISINK = 100mA VCC = 3.3V, ISOURCE = -100mA
(2)
% ns ns ns
2.7 2.4 2.2 1.5 35 27 40
Pull-Down Resistance (DRVL) Output Rise Time Output Fall Time Minimum Non-Overlap (1)
VCC = 3.3V, ISINK = 100mA VCC = 3.3V, COUT = 4.7nF VCC = 3.3V, COUT = 4.7nF
Notes: (1). Guaranteed by design. (2). Guaranteed by characterization.
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SC4607
POWER MANAGEMENT Pin Configuration
Top View
Ordering Information
Part Number SC4607IMSTR SC4607IMSTRT(2) Device MSOP-10
Notes: (1) Only available in tape and reel packaging. A reel contains 2500 devices. (2) Lead free product. This product is fully WEEE and RoHS compliant. (10 Pin MSOP)
Pin Descriptions
Pin # 1 Pin Name BST Pin Function This pin enables the converter to drive an N-Channel high side MOSFET. BST connects to the external charge pump circuit. The charge pump circuit boosts the BST pin voltage to a sufficient gate-to-source voltage level for driving the gate of the high side MOSFET. Positive supply rail for the IC. For improved noise immunity, bypass this pin to GND with a 0.1 to 4.7F low ESL/ESR ceramic capacitor. The ISET pin is used to limit current in the high side MOSFET. The SC4607 uses the voltage across the Vin and ISET pins in order to set the current limit. The current limit threshold is set by the value of an external resistor (R3 in the Typical Application Circuit Diagram). Current limiting is performed by comparing the voltage drop across the sense resistor with the voltage drop across the drain to source resistance of the high side MOSFET during the MOSFET's conduction period. The voltage drop across the drain to source resistance of the high side MOSFET is obtained from the Vin and PHASE pins. This is the output of the voltage amplifier. The voltage at this output is inverted internally and connected to the non-inverting input of the PWM comparator. A lead-lag network from the COMP pin to the VSENSE pin compensates for the two pole LC filter characteristics inherent to voltage mode control. The lead-lag network is required in order to optimize the dynamic performance of the voltage mode control loop. The FS/SYNC pin sets the PWM oscillator frequency through an external timing capacitor that is connected from the FS/SYNC pin to the GND pin. Sleep mode operation is invoked by clamping the FS/SYNC pin to a voltage below 75mV. The typical supply current during sleep mode is 10A. The SC4607 can be operated in synchronous mode by inserting a resistor in series between the timing capacitor and GND pin. The other terminal of the timing capacitor will remain connected to the FS/SYNC pin. This pin is the inverting input of the voltage amplifier and serves as the output voltage feedback point for the Buck converter. VSENSE is compared to an internal reference value of 0.5V. VSENSE is hardwired to the output voltage when an output of 0.5V is desired. For higher output voltages, a resistor divider network is necessary (R7 and R9 in the Typical Application Circuit Diagram). Signal and power ground for the IC. All voltages are measured with respect to this pin. All bypass and timing capacitors connected to GND should have leads as short and direct as possible.
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2 3
VC C ISET
4
COMP
5
FS/SYNC
6
VSENSE
7
GND
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SC4607
POWER MANAGEMENT Pin Descriptions (Cont.)
Pin # 8 Pin Name DRVL Pin Function Gate drive pin. DRVL drives the gate of the low side (synchronous rectifier) MOSFET. The output driver is rated for 1A peak current. The PWM circuitry provides complementary drive signals to the output stages. The cross conduction of the external MOSFETs is prevented by monitoring the voltage on the DRVH and DRVL driver pins of the MOSFET pair in conjunction with a time delay optimized for FET turn-off characteristics The PHASE pin is used to limit current in the high side MOSFET. The SC4607 uses the voltage across the Vin and ISET pins in order to set the current limit. The current limit threshold is set by the value of an external resistor (R3 in the Typical Application Circuit Diagram). Current limiting is performed by comparing the voltage drop across the sense resistor with the voltage drop across the drain to source resistance of the high side MOSFET during the MOSFET's conduction period. The voltage drop across the drain to source resistance of the high side MOSFET is obtained from the Vin and PHASE pins. Gate drive pin. DRVH drives the gate of the high side (main switch) MOSFET. The output driver is rated for 1A peak current. The PWM circuitry provides complementary drive signals to the output stages. The cross conduction of the external MOSFETs is prevented by monitoring the voltage on the DRVH and DRVL driver pins of the MOSFET pair in conjunction with a time delay optimized for FET turn-off characteristics
9
PHASE
10
DRVH
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SC4607
POWER MANAGEMENT Block Diagram
Marking Information
4607
nnnn = Part Number (Example: 1456) yyww = Datecode (Example: 0012) xxxx = Semtech Lot # (Example: E901 xxxx 01-1)
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SC4607
POWER MANAGEMENT Typical Characteristics
Oscillator Internal Accuracy vs Input Voltage
588 586 584 582 580 578 576 574 2.5 584 583 582 581 580 579 578 577 -40
Internal Accuracy (kHz) Internal Accuracy (kHz)
Oscillator Internal Accuracy vs Temperature
TA = 25C
Vcc = 3.3V
3
3.5
4
Vcc (V)
4.5
5
5.5
-20
0
20
40
60
80
Temperature (C)
Sense Voltage vs Input Voltage
500.0 499.9 499.8 499.7 499.6 499.5 499.4 2.5
Sense Voltage (mV) Sense Voltage (mV)
Sense Voltage vs Temperature
500.5 500.0 499.5 499.0 498.5 498.0 -40
Vcc = 3.3V
TA = 25C
3
3.5
4
Vcc (V)
4.5
5
5.5
-20
0
20
Temperature (C)
40
60
80
Current Limit Bias Current vs Input Voltage
55 Current Limit Bias Current (uA) 54 53 52 51 50 2.5 3 3.5 4 Vcc (V) 4.5 5 5.5
Current Limit Bias Current vs Temperature
65 60 55 50 45 40 -40 -20 0 20
Temperature (C)
Current Limit Bias Current (uA)
TA = 25C
Vcc = 3.3V
40
60
80
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SC4607
POWER MANAGEMENT Application Information
Enable: The SC4607 is enabled by applying a voltage greater than 2.25 volts to the VCC pin. The SC4607 is disabled when VCC falls below 1.95 volts or when sleep mode operation is invoked by clamping the FS/SYNC pin to a voltage below 75mV. 10A is the typical current drawn through the VCC pin during sleep mode. During the sleep mode, the high side and low side MOSFETs are turned off and the internal soft start voltage is held low. Oscillator: The FS/SYNC pin is used to set the PWM oscillator frequency through an external timing capacitor that is connected from the FS/SYNC pin to the GND pin. The resulting ramp waveform on the FS/SYNC pin is a triangle at the PWM frequency with a peak voltage of 1.3V and a valley voltage of 0.3V. The PWM duty ratio is limited by the ramp to a maximum of 97%, which allows the bootstrap capacitor to be charged during each cycle. The capacitor tolerance adds to the accuracy of the oscillator frequency. The approximate operating frequency and soft start time are both determined by the value of the external timing capacitor as shown in Table 1. then connected to the junction of the external timing capacitor and the added resistor as shown in Figure 1.
SC4607
FS/SYNC Ctiming External Clock Signal
Rsync 100 ohm
Figure 1 UVLO: When the FS/SYNC pin is not pulled and held below 75mV, the voltage on the Vcc pin determines the operation of the SC4607. As Vcc increases during start up, the UVLO block senses Vcc and keeps the high side and low side MOSFETs off and the internal soft start voltage low until Vcc reaches 2.25V. If no faults are present, the SC4607 will initiate a soft start when Vcc exceeds 2.25V. A hysteresis (100mV) in the UVLO comparator provides noise immunity during its start up. Soft Start:
External Timing Capacitor Value (pF) 120 270 560
Frequency (kHz ) 1000 580 350
Soft Start Time (s)
628 1220 1838
Table 1: Operating Frequency and Soft Start Time Values Based On the Value of the External Timing Capacitor Placed Across the FS/SYNC and GND Pins Synchronous mode operation is invoked by using a signal from an external clock. A low value resistor (100 typical) must be inserted in series with the timing capacitor between the timing capacitor and the GND pin. The other terminal of the timing capacitor will remain connected to the FS/SYNC pin. The external clock signal is
The soft start function is required for step down controllers to prevent excess inrush current through the DC bus during start up. Generally this can be done by sourcing a controlled current into a timing capacitor and then using the voltage across this capacitor to slowly ramp up the error amp reference. The closed loop creates narrow width driver pulses while the output voltage is low and allows these pulses to increase to their steady state duty cycle as the output voltage reaches its regulated value. With this, the inrush current from the input side is controlled. The duration of the soft start in the SC4607 is controlled by an internal timing circuit which is used during start up and over current to set the hiccup time. The soft start time can be obtained from Table 1. The SC4607 implements its soft start by ramping up the error amplifier reference voltage providing a controlled
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SC4607
POWER MANAGEMENT Application Information (Cont.)
slew rate of the output voltage, then preventing overshoot and limiting inrush current during its start up. During start up of a converter with a big capacitive load, the load current demands large supply current. To avoid this an external soft start scheme can be implemented as shown in Figure 2. Cs can be adjusted for different applications.
Cs
current protection. Because the RDS(ON) has a positive temperature coefficient, the 50A current source has a positive coefficient of about 0.28%/C providing first order correction for current sensing vs temperature. This compensation depends on the high amount of thermal transferring that typically exists between the high side NMOSFET and the SC4607 due to the compact layout of the power supply. When the converter detects an over current condition (I > IMAX) as shown in Figure 3, the first action the SC4607 takes is to enter the cycle by cycle protection mode (Point B to Point C), which responds to minor over current cases. Then the output voltage is monitored. If the over current and low output voltage (set at 70% of nominal output voltage) occur at the same time, the Hiccup mode operation (Point C to Point D) of the SC4607 is invoked and the internal soft start capacitor is discharged. This is like a typical soft start cycle:
Pin COMP
Rs 2.05k Rp 47.5k Q MMBT2222A-7
Vo Output of a converter
330n
Figure 2 Over Current Protection: The SC4607 detects over current conditions by sensing the voltage across the drain-to-source of the high side MOSFET. The SC4607 determines the high side MOSFET current level by sensing the drain-to-source conduction voltage across the high side MOSFET via the Vin (see the Typical Application Circuit on page 1) and PHASE pin during the high side MOSFET's conduction period. This voltage value is then compared internally to a user programmed current limit threshold. Note that user should place Kelvin sensing connections directly from the high side MOSFET source to the PHASE pin. The current limit threshold is programmed by the user based on the RDS(on) of the high side MOSFET and the value of the external set resistor RSET (where RSET is represented by R3 in the applications schematics of this document). The SC4607 uses an internal current source to pull a 50A current from the input voltage to the ISET pin through external resistor RSET. The current limit threshold resistor (RSET) value is calculated using the following equation:
V O - nom
A
B
0 .6 VO - nom
C
VO
0.7
D
IO
IMAX
Figure 3. Over current protection characteristic of SC4607 Power MOSFET Drivers: The SC4607 has two drivers which are optimized for driving external power N-Channel MOSFETs.. The driver block consists two 1 Amp drivers. DRVH drives the high side N-MOSFET (main switch), and DRVL drives the low side N-MOSFET (synchronous rectifier transistor). The output drivers also have gate drive non-overlap mechanism that provides a dead time between DRVH and DRVL transitions to avoid potential shoot through problems in the external MOSFETs. By using the proper design and the appropriate MOSFETs, the SC4607 is capable of driving a converter with up to 12A of output
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R SET =
IMAX R DS( ON) 50A
The RDS(ON) sensing used in the SC4607 has an additional feature that enhances the performance of the over
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SC4607
POWER MANAGEMENT Application Information (Cont.)
current. As shown in Figure 4, t the delay from the d1, top MOSFET off to the bottom MOSFET on is adaptive by detecting the voltage of the phase node. t , the delay d2 from the bottom MOSFET off to the top MOSFET on is fixed, is 40ns for the SC4607. This control scheme guarantees avoidance of cross conduction or shoot through between the upper and lower MOSFETs and also minimizes the conduction loss in the body diode of the bottom MOSFET for high efficiency applications.
The peak to peak inductor current is:
Ip -p = I * IOMAX
After the required inductor value is selected, the proper selection of the core material is based on the peak inductor current and efficiency requirements. The core must be able to handle the peak inductor current IPEAK without saturation and produce low core loss during the high frequency operation is:
IPEAK = IOMAX + Ip -p 2
TOP MOSFET Gate Drive BOTTOM MOSFET Gate Drive
Phase node
Ground
td1
td2
The power loss for the inductor includes its core loss and copper loss. If possible, the winding resistance should be minimized to reduce inductor's copper loss. The core loss can be found in the manufacturer's datasheet. The inductor' copper loss can be estimated as follows:
PCOPPER = I2LRMS R WINDING
Figure 4. Timing Waveforms for Gate Drives and Phase Node Inductor Selection: The factors for selecting the inductor include its cost, efficiency, size and EMI. For a typical SC4607 application, the inductor selection is mainly based on its value, saturation current and DC resistance. Increasing the inductor value will decrease the ripple level of the output voltage while the output transient response will be degraded. Low value inductors offer small size and fast transient responses while they cause large ripple currents, poor efficiencies and more output capacitance to smooth out the large ripple currents. The inductor should be able to handle the peak current without saturating and its copper resistance in the winding should be as low as possible to minimize its resistive power loss. A good tradeoff among its size, loss and cost is to set the inductor ripple current to be within 15% to 30% of the maximum output current. The inductor value can be determined according to its operating point and the switching frequency as follows:
L= Vout ( Vin - Vout ) Vin fs I IOMAX
Where: ILRMS is the RMS current in the inductor. This current can be calculated as follow is:
ILRMS = IOMAX 1 + 1 I2 3
Output Capacitor Selection: Basically there are two major factors to consider in selecting the type and quantity of the output capacitors. The first one is the required ESR (Equivalent Series Resistance) which should be low enough to reduce the voltage deviation from its nominal one during its load changes. The second one is the required capacitance, which should be high enough to hold up the output voltage. Before the SC4607 regulates the inductor current to a new value during a load transient, the output capacitor delivers all the additional current needed by the load. The ESR and ESL of the output capacitor, the loop parasitic inductance between the output capacitor and the load combined with inductor ripple current are all major contributors to the output voltage ripple. Surface mount speciality polymer aluminum electrolytic chip capacitors in UE series from Panasonic provide low ESR and reduce the total capacitance required for a fast transient response. POSCAP from Sanyo is a solid electrolytic chip capacitor that has a low ESR and good performance for high frequency with a low profile and high capacitance. Above mentioned capacitors are recommended to use in
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Where: fs = switching frequency and I = ratio of the peak to peak inductor current to the maximum output load current.
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SC4607
POWER MANAGEMENT Application Information (Cont.)
SC4607 application: Input Capacitor Selection: The input capacitor selection is based on its ripple current level, required capacitance and voltage rating. This capacitor must be able to provide the ripple current by the switching actions. For the continuous conduction mode, the RMS value of the input capacitor can be calculated from:
ICIN(RMS ) = IOMAX Vout ( Vin - Vout ) 2 Vin
Where: fs = the switching frequency and Dmax = maximum duty ratio, 0.97 for the SC4607. The required minimum capacitance for boost capacitor will be:
Cboost = IB TW VD
Where: IB = the boost current and VD= discharge ripple voltage. With fs = 300kH, VD=0.3V and IB=50mA, the required capacitance for the boost capacitor is:
Cboost = IB 1 0.05 1 Dmax = 0.97 = 540nF VD fs 0.3 300k
This current gives the capacitor's power loss as follows:
PCIN = I2 CIN(RMS ) R CIN(ESR )
This capacitor's RMS loss can be a significant part of the total loss in the converter and reduce the overall converter efficiency. The input ripple voltage mainly depends on the input capacitor's ESR and its capacitance for a given load, input voltage and output voltage. Assuming that the input current of the converter is constant, the required input capacitance for a given voltage ripple can be calculated by:
CIN = IOMAX D (1 - D) fs ( VI - IOMAX R CIN(ESR ) )
Power MOSFET Selection: The SC4607 can drive an N-MOSFET at the high side and an N-MOSFET synchronous rectifier at the low side. The use of the high side N-MOSFET will significantly reduce its conduction loss for high current. For the top MOSFET, its total power loss includes its conduction loss, switching loss, gate charge loss, output capacitance loss and the loss related to the reverse recovery of the bottom diode, shown as follows:
ITOP _ PEAK Vin fs VGATE RG
Where: D = Vout/Vin , duty ratio and VI = the given input voltage ripple. Because the input capacitor is exposed to the large surge current, attention is needed for the input capacitor. If tantalum capacitors are used at the input side of the converter, one needs to ensure that the RMS and surge ratings are not exceeded. For generic tantalum capacitors, it is wise to derate their voltage ratings at a ratio of 2 to protect these input capacitors. Boost Capacitor Selection: The boost capacitor selection is based on its discharge ripple voltage, worst case conduction time and boost current. The worst case conduction time Tw can be estimated as follows:
Tw = 1 Dmax fs
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PTOP _ TOTAL = I2 TOP _ RMS R TOP _ ON +
(QGD + QGS 2 ) + QGT VGATE fs + (QOSS + Qrr ) Vin fs
Where: RG = gate drive resistor, QGD = the gate to drain charge of the top MOSFET, QGS2 = the gate to source charge of the top MOSFET, QGT = the total gate charge of the top MOSFET, QOSS = the output charge of the top MOSFET and Qrr = the reverse recovery charge of the bottom diode. For the top MOSFET, it experiences high current and high voltage overlap during each on/off transition. But for the
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SC4607
POWER MANAGEMENT Application Information (Cont.)
bottom MOSFET, its switching voltage is the body diode's forward drop of the bottom MOSFET during its on/off transition. So the switching loss for the bottom MOSFET is negligible. Its total power loss can be determined by:
PBOT _ TOTAL = I2 BOT _ RMS R BOT _ ON + Q GB VGATE fs + ID _ AVG VF
voltage according to
Vout = 0.5 (1 + R7 ) R9
BST VCC
DRVH PHASE DRVL GND VSENSE
L1
Vout
Where: QGB = the total gate charge of the bottom MOSFET and VF = the forward voltage drop of the body diode of the bottom MOSFET. For a low voltage and high output current application such as the 3.3V/1.5V@12A case, the conduction loss is often dominant and selecting low RDS(ON) MOSFETs will noticeably improve the efficiency of the converter even though they give higher switching losses. The gate charge loss portion of the top/bottom MOSFET's total power loss is derived from the SC4607. This gate charge loss is based on certain operating conditions (fs, VGATE, and IO). The thermal estimations have to be done for both MOSFETs to make sure that their junction temperatures do not exceed their thermal ratings according to their total power losses PTOTAL, ambient temperature TA and their thermal resistance R JA as follows:
ISET COMP C1 C2 FS/SY NC
C9 R7 C4 R
SC4607
R1
R8
Figure 4. Compensation network provides 3 poles and 2 zeros.
R9
Figure 5. Compensation network provides 3 poles and 2 zeros. For voltage mode step down applications as shown in Figure 5, the power stage transfer function is:
1+ G VD (s) = VI s 1 RC C4
1+ s
L1 + s 2L 1C 4 R
TJ(max) < TA +
PTOTAL R JA
Loop Compensation Design: For a DC/DC converter, it is usually required that the converter has a loop gain of a high cross-over frequency for fast load response, high DC and low frequency gain for low steady state error, and enough phase margin for its operating stability. Often one can not have all these properties at the same time. The purpose of the loop compensation is to arrange the poles and zeros of the compensation network to meet the requirements for a specific application. The SC4607 has an internal error amplifier and requires the compensation network to connect among the COMP pin and VSENSE pin, GND, and the output as shown in Figure 5. The compensation network includes C1, C2, R1, R7, R8 and C9. R9 is used to program the output
Where: R = load resistance and RC = C4's ESR. The compensation network will have the characteristic as follows:
s s 1+ Z1 Z 2 GCOMP (s) = I s s s 1+ 1+ P1 P 2 1+
Where
I = 1 R 7 ( C1 + C 2 ) 1 R1 C 2
Z1 = Z 2 =
1 (R 7 + R 8 ) C 9
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SC4607
POWER MANAGEMENT Application Information (Cont.)
P1 = C1 + C 2 R 1 C1 C 2 1 R 8 C9
Layout Guidelines: In order to achieve optimal electrical, thermal and noise performance for high frequency converters, special attention must be paid to the PCB layouts. The goal of layout optimization is to identify the high di/dt loops and minimize them. The following guideline should be used to ensure proper functions of the converters. 1. A ground plane is recommended to minimize noises and copper losses, and maximize heat dissipation. 2. Start the PCB layout by placing the power components first. Arrange the power circuit to achieve a clean power flow route. Put all the connections on one side of the PCB with wide copper filled areas if possible. 3. The Vcc bypass capacitor should be placed next to the Vcc and GND pins. 4. The trace connecting the feedback resistors to the output should be short, direct and far away from the noise sources such as switching node and switching components. 5. Minimize the traces between DRVH/DRVL and the gates of the MOSFETs to reduce their impedance to drive the MOSFETs. 6. Minimize the loop including input capacitors, top/bottom MOSFETs. This loop passes high di/dt current. Make sure the trace width is wide enough to reduce copper losses in this loop. 7. ISET and PHASE connections to the top MOSFET for current sensing must use Kelvin connections. 8. Maximize the trace width of the loop connecting the inductor, bottom MOSFET and the output capacitors. 9. Connect the ground of the feedback divider and the compensation components directly to the GND pin of the SC4607 by using a separate ground trace. Then connect this pin to the ground of the output capacitor as close as possible
P 2 =
After the compensation, the converter will have the following loop gain:
s 1+ 1 s s 1 I VI 1 + 1+ RC C 4 Z1 Z 2 VM T(s) = GPWM GCOMP (s) G VD (s) = s s L s 1+ 1+ 1 + s 1 + s 2L1C P1 P 2 R
Where: GPWM = PWM gain VM = 1.0V, ramp peak to valley voltage of SC4607 The design guidelines for the SC4607 applications are as following: 1. Set the loop gain crossover corner frequency C for given switching corner frequency S = 2fs, 2. Place an integrator at the origin to increase DC and low frequency gains. 3. Select Z1 and Z2 such that they are placed near O to damp the peaking and the loop gain has a -20dB/dec rate to go across the 0dB line for obtaining a wide bandwidth. 4. Cancel the zero from C4's ESR by a compensator pole P1 (P1 = ESR = 1/( RCC4)). 5. Place a high frequency compensator pole p2 (p2 = fs) to get the maximum attenuation of the switching ripple and high frequency noise with the adequate phase lag at C. The compensated loop gain will be as given in Figure 6:
T(s) z1 Gvd 0dB Power stage GVD(s) ESR -40dB/dec o z2 c p1 p2 -20dB/dec Loop gain T(s)
Figure 6. Asymptotic diagrams of power stage and its loop gain.
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SC4607
POWER MANAGEMENT Application Information (Cont.)
Design Example 1: 3.3V to1.5V @12A application with SC4607
Vin=3.3V
C13 D2 R3 R13 1 C71 1u 0 DRVH PHASE DRVL GND VSENSE 10 9 8 7 6 0 R5 M2 2.3u C7 330u C5 22u C4 22u C9 5.6n R8 169 R7 8.25k R6 M1 100u C14 100u C10 22u C11 22u
U1 1 C3 4.7u 2 3 4 C1 270p R1 14.3k C2 2.2n C16 560pF 5 BST VCC ISET COMP FS/SY NC
L1
Vo=1.5V/12A
SC4607
R9 4.12k
Design Example 2: 3.3V to 2.5V @ 20A application with SC4607
2 x 4TPE150M
C10 D2 150u 1u C17 C11 150u C13 22u C14 22u
Vin=3.3V
4 x C3216X5R0J226M
M11 M12
R3 1.05k
C18 0.1u
R13 1 U1 1 C3 4.7u 2 3 4 BST VCC ISET COMP FS/SY NC DRVH PHASE DRVL GND VSENSE 10 9 8 7 6
R6 0 R5 0 M21 M22
ETQPAF1R3EA
L1 1.3u C7 330u C5 22u C4 22u
Vo=2.5V/20A
C2 C1 270p
1.5n
C16 560pF
C9 2.7n R8 365 R7 16.5k
5
SC4607
R1 20k
4 x Si7882
4TPD330M
R9 4.12k
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SC4607
POWER MANAGEMENT Bill of Materials - 3.3V to 1.5V @ 12A
Item 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 Qty 1 1 1 4 1 1 1 1 1 1 2 1 1 2 1 1 1 1 1 2 1 C1 C2 C 17 C4,C5, C10, C11 C7 C9 C 18 C 16 D2 L1 M1,M2 R1 R3 R5, R6 R7 R8 R9 R13 C3 C13,C14 U1 Reference 270pF 2.2nF 1uF 22uF, 1210 330uF, 2870 5.6nF 0.1nF 560pF MBR0520LT1 2.3uH Powerpack, SO-8 14.3K 1.4K 0 8.25K 169 4.12K 1 4.7uF, 0805 100uF, 2870 S C 4607 Sanyo P/N: 6TPB100M Semtech P/N: SC4607IMSTR ON Semi P/N: MBR0520LT1 Cooper Electronic P/N: HC1-2R3 Vishay P/N: Si7882DP TDK P/N: C3225X5R0J226M Sanyo P/N: 6TPD330M Value Part No./Manufacturer
Unless specified, all resistors and capacitors are in SMD 0603 package. Resistors are +/-1% and all capacitors are +/-20%
2005 Semtech Corp.
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SC4607
POWER MANAGEMENT PCB Layout - 3.3V to 1.5V @ 12A
TOP
TOP
BOTTOM
BOTTOM
2005 Semtech Corp.
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SC4607
POWER MANAGEMENT Outline Drawing - MSOP-10
e A N 2X E/2 PIN 1 INDICATOR ccc C 2X N/2 TIPS 12 B E1 E D
DIM
A A1 A2 b c D E1 E e L L1 N 01 aaa bbb ccc
DIMENSIONS INCHES MILLIMETERS MIN NOM MAX MIN NOM MAX
.043 .000 .006 .030 .037 .007 .011 .003 .009 .114 .118 .122 .114 .118 .122 .193 BSC .020 BSC .016 .024 .032 (.037) 10 8 0 .004 .003 .010 1.10 0.00 0.15 0.95 0.75 0.17 0.27 0.08 0.23 2.90 3.00 3.10 2.90 3.00 3.10 4.90 BSC 0.50 BSC 0.40 0.60 0.80 (.95) 10 0 8 0.10 0.08 0.25
D aaa C SEATING PLANE A2 C A1 bxN bbb C A-B D A GAGE PLANE 0.25 (L1) DETAIL SIDE VIEW
NOTES: 1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES). 2. DATUMS -A- AND -B- TO BE DETERMINED AT DATUM PLANE -H3. DIMENSIONS "E1" AND "D" DO NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. 4. REFERENCE JEDEC STD MO-187, VARIATION BA.
H c
L
01
A
SEE DETAIL
A
Land Pattern - MSOP-10
X
DIM
(C) G Z C G P X Y Z
DIMENSIONS INCHES MILLIMETERS
(.161) .098 .020 .011 .063 .224 (4.10) 2.50 0.50 0.30 1.60 5.70
Y P
NOTES: 1. THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY. CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR COMPANY'S MANUFACTURING GUIDELINES ARE MET.
Contact Information
Semtech Corporation Power Management Products Division 200 Flynn Road, Camarillo, CA 93012 Phone: (805)498-2111 FAX (805)498-3804
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